In a recent industry interview, SMIC co-founder Xie Zhifeng stated that China can now produce logic chips with 5nm-class performance using DUV multipatterning and 3D stacking, without relying on EUV lithography. SMIC has moved beyond conventional node labeling with its N+1, N+2, and N+3 processes – and he emphasized that real-world system performance, not process node names, is what matters.

While DUV multipatterning enables equivalent 7nm and 5nm capability, Xie acknowledged key limitations: the process dramatically extends production cycles and multiplies costs, making it impractical for high-volume manufacturing – better suited for small-batch prototyping and specialized chips.

He also cautioned against the node number obsession , citing Samsung's 5nm Snapdragon 888 and 4nm Snapdragon 8 Gen 1 – both advanced on paper but plagued by heat and power issues. "Smaller node does not always mean better chip," he noted.

Xie expressed strong confidence in China's semiconductor future, highlighting domestic engineering talent and the ability to forge a self-reliant development path using available resources.

From ICgoodFind: 5nm without EUV? Yes – but at a cost. Multipatterning works, but it's a design-to-manufacturing trade-off that changes what "advanced" really means.